1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, it relates to a semiconductor integrated circuit device wherein a main memory unit and an auxiliary memory unit are formed on the same semiconductor substrate and a data transfer circuit is provided between the main memory unit and the auxiliary memory unit.
2. Description of the Related Art
Large-capacity semiconductor devices which are comparatively slow and inexpensive are commonly employed as the main memory devices used in computer systems; common DRAMs, which meet these requirements, are widely employed in this way.
Furthermore, attempts have recently been made in computer systems to increase the speed of the DRAMs which comprise the main memory units in response to an increase in speed of the system (in particular, an increase in speed of the MPU); however, this is insufficient with respect to the increase in speed of the MPU, and most systems incorporate a high-speed memory between the MPU and the main memory unit as an auxiliary memory unit. These auxiliary memory units are commonly termed cache memories, and high speed SRAMs or ECLRAMs or the like are commonly employed as such cache memories.
Actually installed cache memories include those which are provided outside the MPU and those which are installed within the MPU; recently, semiconductor memory devices have attracted attention in which the DRAM which comprises the main memory unit and the cache memory are installed on the same semiconductor substrate. Conventional examples thereof include those disclosed in, for example, Japanese Patent Application, First Publication No. SHO 57-20983, Japanese Patent Application, First Publication No. SHO 60-7690, Japanese Patent Application, first publication No. SHO 62-38590, and Japanese Patent Application, First Publication No. HEI 1-146187. These preceding technology semiconductor memory devices have both a DRAM and cache memory installed, and have come to be termed by some cache DRAMs. Furthermore, they are also termed CDRAM. These have a structure in which data may be transferred in both directions between the SRAM which functions as the cache memory and the DRAM which functions as the main memory unit.
This preceding technology had problems, such as a delay in the data transfer operation during cache mishits, so that improved technology was proposed. The improved conventional technology was that described below. For example, in the technology disclosed in Japanese Patent Application, First Publication No. HEI 4-252486, Japanese Patent Application, First Publication No. HEI 4-318389, and Japanese Patent Application, First Publication No. HEI 5-2872, the characteristic feature was that a latch or a register function was provided in the bidirectional data transfer circuit which served to conduct data transfer between the DRAM and SRAM unit; this was capable of simultaneously conducting data transfer from the SRAM to the DRAM unit and from the DRAM unit to the SRAM unit, and enabled an increase in data transfer (copy back) speed during cache mishits.
This technology will be explained using as an example that disclosed in Japanese Patent Application, First Publication No. HEI 4-318389.
FIG. 17 shows, in schematic form, an example of the structure of an CDRAM memory array unit. In FIG. 17, the semiconductor memory devices contains a DRAM array 9201 which contains dynamic type memory cells, and an SRAM array 9202 which contains static type memory cells, and a bidirectional transfer gate circuit 9203, which serves to conduct data transfer between the DRAM array 9201 and the SRAM array 9202. Furthermore, each of the DRAM array 9201 and the SRAM array 9202 are provided with a corresponding row decoder and column decoder. The addresses assigned to the row decoder and column decoder of the DRAM and the row decoder and column decoder of the SRAM are independent of one another, and the structure is such that this assignment is conducted via differing address pin terminals. FIGS. 18 and 19 show the details of the structure of the bidirectional transfer gate circuit 9203. By means of the structure depicted, the data transfer from SBL to the GIO and the data transfer from the GIO to the SBL employ differing data transfer paths, and as a result of the function of the latch 9305 and amplifier 9306, it is possible to execute these data transfers in an overlapping fashion.
In semiconductor integrated devices, among functions which relate to the entirety of the package, a decrease in power consumption and an increase in operational speed are commonly desired. In general, when the operating voltage is increased, it is possible to achieve an increase in operating speed; however, as a result, the power consumption tends to rise. When on the other hand, the operational voltage is set at a low level in order to achieve a reduction in power consumption, this entails a sacrifice of operating speed.
In CDRAMs employing the conventional technology described above, in order to achieve a reduction in power consumption, the operating voltage of the DRAM which serves as the main memory unit is set at a low level, while in contrast, the operating voltage of the SRAM which functions as a cache memory and forms the auxiliary memory unit is set at a high level to accommodate the requirement of an increase in speed.
The bidirectional transfer gate circuit depicted in FIG. 17 is extremely important in order to conduct data transfer between the main memory unit and the auxiliary memory unit, which have differing operational power levels. The reason for this is that, in semiconductor memory circuit devices in which a cache memory such as that described above is installed, because the operating voltage of the main memory unit is low, there are cases in which a plurality of processes must be executed simultaneously, such as when data transfer is conducted in an overlapping manner as in the case of the CDRAM described above, and in such cases, the internal noise generated as a consequence of the operation of the circuitry reaches a high level and this tends to result in operational errors within the circuitry. In particular, in cases in which an DRAM which handles extremely weak data signals is employed as the chief memory unit, it is necessary to effectively suppress the internal noise generated. In this situation, problems are caused even when data transfer is conducted between the main memory unit and the auxiliary memory unit.
Furthermore, in recent years, an increase in operational speed has been required of semiconductor integrated circuit devices, as described above; however, if data transfer can not be efficiently conducted between a main memory unit and an auxiliary memory unit which have different operational voltages, it is impossible to obtain an increase in operating speed.
The present invention was created in light of the above circumstances; it has as an object thereof to provide a semiconductor integrated circuit device which is capable of efficiently conducting data transfer between a main memory unit and an auxiliary memory unit which operate at different operational voltages, and moreover, is capable of operating in a stable manner while effectively suppressing internal noise which is generated.
In order to solve the problem described above, a first semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit which functions as a cache memory and has a structure in which bidirectional data transfer is possible via a data transfer bus line which is provided between the main memory unit and the auxiliary memory unit, and furthermore, this device is provided with a power source mechanism which supplies to the data transfer bus line, when data is not being transferred, a voltage which is lower than the power source voltage supplied to the main memory unit.
The device of the present invention may be provided with a sense amplifier circuit which is provided in the main memory unit, and a sense amplifier unit control circuit for controlling this sense amplifier circuit; the sense amplifier unit control circuit supplies, to the connecting circuit which serves to connect the sense amplifier circuit and the data transfer bus line, a main memory unit power source level, when data is transferred from the main memory unit to the auxiliary memory unit, and a main memory unit increased voltage power source level, which represents an increase in the main memory unit power source level, when data is transferred from the auxiliary memory unit to the main memory unit.
Furthermore, the device of the present invention may be provided with a plurality of memory cells provided in the auxiliary memory unit, and an auxiliary memory unit control circuit for controlling the auxiliary memory unit; this auxiliary memory unit control circuit supplies, to the connecting circuit which connects the memory cells and the data transfer bus line, a main memory unit increased voltage power source level, which represents an increase in the main memory unit power source level, when data transferred from the main memory unit are to be incorporated, and supplies the main memory unit power source level when data are to be transferred from the memory cells to the main memory unit.
Furthermore, in the device of the present invention, when data transferred from the auxiliary memory unit are to be incorporated, it is preferable that the sense amplifier unit control circuit place the transistors provided within the sense amplifier circuit in a non-conductive state prior to incorporation.
Furthermore, in the device of the present invention, when data transferred from the main memory unit are to incorporated, it is preferable that the auxiliary memory unit control circuit place the transistors provided within the memory cells in a non-conducting state prior to incorporation.
A second semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit, and has a structure such that bidirectional data transfer is possible via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit, and is further provided with:
sense amplifier circuits which are provided in the main memory unit,
a sense amplifier unit control circuit for controlling the sense amplifier circuits, and
a switch mechanism for electrically connecting the sense amplifier circuits and the main memory memory cells within the main memory unit;
after the data transferred from the main memory unit to the auxiliary memory unit have been incorporated into the sense amplifier circuits, the sense amplifier unit control circuit controls the switch mechanism and electrically disconnects the sense amplifier circuits and the main memory unit memory cells, and in this disconnected state, the data are transferred from the main memory unit to the auxiliary memory unit.
The sense amplifier unit control circuit may, in parallel with the amplification of the data incorporated into the sense amplifier circuits, control the switch mechanism and electrically disconnect the sense amplifier circuits and the main memory unit memory cells, and may transfer the data when a transfer initiation command for initiating data transfer from the main memory unit to the auxiliary memory unit is inputted in the state in which the sense amplifier circuits and the main memory unit memory cells are electrically disconnected.
Furthermore, the sense amplifier unit control circuit may conduct the amplification of the data incorporated into the sense amplifier circuits and, when a transfer initiation command for initiating data transfer from the main memory unit to the auxiliary memory unit has been inputted, electrically disconnect the sense amplifier circuits from the main memory unit memory cells, and may transfer the data in the state in which the sense amplifier circuits are electrically disconnected from the main memory unit memory cells.
Furthermore, the operation initiation command, which activates the main memory unit, and the transfer operation initiation command, which initiates data transfer from the main memory unit to the auxiliary memory unit, may be inputted at the same timing.
Furthermore, the sense amplifier unit control circuit may control the switch mechanism at the termination of transfer and electrically connect the sense amplifier circuits with the main memory unit memory cells.
The auxiliary memory unit may be divided into a plurality of auxiliary memory unit memory cell rows, and when transfer to the plurality of auxiliary memory unit memory cell rows is terminated, the sense amplifier unit control circuit may control the switch mechanism and electrically connect the sense amplifier circuits with the main memory unit memory cells.
A third semiconductor integrated circuit device of the present invention is provided with a main memory unit and an auxiliary memory unit and has a structure such that bidirectional data transfer is possible via data transfer bus lines which are provided between the main memory unit and the auxiliary memory unit, and this device is further provided with:
sense amplifier circuits which are provided in the main memory unit, and
a sense amplifier unit control circuit for controlling the sense amplifier circuit; wherein
the sense amplifier circuits have a segmented structure in which a plurality are provided with respect to each data transfer bus line, and
the sense amplifier unit control circuit electrically connects one sense amplifier circuit to each data transfer bus line, and, prior to conducting data transfer from the auxiliary memory unit to the main memory unit, carries out an amplification operation with respect to those sense amplifier circuits which are not connected to data transfer bus lines.
The sense amplifier circuits are provided with balance precharge circuits, and
the sense amplifier unit control circuit may have a mechanism for controlling the balance precharge circuit of each segment.
Furthermore, the sense amplifier circuits may be provided with switch mechanisms for electrically connecting the sense amplifier circuits with the main memory unit memory cells in the main memory unit, and the sense amplifier unit control circuit may, when data transfer is conducted from the auxiliary memory unit to the main memory unit, electrically disconnect the sense amplifier circuits from the main memory unit memory cells.
In accordance with the present invention, when data is not transferred, a voltage having a level lower than the power source voltage supplied to the main memory unit is supplied to the data transfer bus lines, and thereby, it is possible to conduct stable operations while effectively suppressing the interior noise generated.
Furthermore, during the transfer of data from the main memory unit to the auxiliary memory unit or from the auxiliary memory unit to the main memory unit, the voltage provided to the connecting circuit connecting the sense amplifier circuits and the data transfer bus lines and to the connecting circuits connecting the memory cells and the data transfer bus lines are varied, so that it is possible to efficiently conduct data transfer between a main memory unit and an auxiliary memory unit which operate at differing operational voltages.
Furthermore, by adjusting the timing of the electrical disconnection of the sense amplifier circuits and the main memory unit memory cells, and the amplification operation of the data incorporated into the sense amplifier circuits, and by making the input timing of the operation initiation command and the transfer operation initiation command identical, application is possible even in cases in which the operational frequency is high.